The general background to the present invention is a processing unit, which sends and receives the information required by a protocol (e.g. SSCOP, #7, HDLC, internal transport protocol, etc.). Such processing units are integrated in many networks, to allow the transfer of data within the network.
Technical developments mean that the requirements relating to processing units are ever more stringent. For example protocol information has to be sent and received in increasingly short time units. This can be achieved on the one hand by minimizing the time required for a transmission operation and on the other hand by increasing the number of transmission channels.
To minimize the time required for a transmission operation, the protocol information is transported using high-performance switching technology, e.g. Asynchronous Transfer Mode (ATM).
Increasing the number of transmission channels in a processing unit for sending and receiving protocol information (currently approx. 16000) gives rise in some instances to management problems, as it is virtually impossible to support a corresponding number of transmission channels in the conventional manner.
In order to be able to support all channels, the protocol must be set up in the hardware, for example via an ASIC (Application Specific Integrated Circuit) and/or an FPGA (Field Programmable Gate Array).
ASICs are special chips, which are designed and optimized on the strength of specific deployment, to achieve a high level of performance.
To optimize the circuit design of said chips, the trend in recent years has moved away from the conventional digital circuit design with standard logic (74xx) to programmable logic. FPGA in particular has gained in significance as a result.
ATM and ASIC have been combined for the transmission of information since the end of the nineties. The combination is used successfully for example in the digital telephone switching system EWSD (Electronic Worldwide Switch Digital).
During the transmission of information what is known as a work split defines which part of the protocol is processed by the ASIC and which part of the protocol is processed by the subsequent software in the processor on the assembly.
Networks are generally tested before the actual transmission of useful data. It is however not possible due to the complexity of the protocols to test the processing of all situations beforehand. A certain error probability therefore always remains. This can mean that in some circumstances defective protocol information is received, which results in total failure of the system. The other transmission channels are thereby also affected.
If an error occurs in an ASIC, the following problems can potentially occur during error correction:
error location is extremely difficult in a complex ASIC,
immediate error rectification is not possible or is only possible by redesign, and
protocol processing can only be restarted by resetting the hardware.
There is therefore a need for a method, which prevents total failure (deadlock) during protocol processing.